W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 6

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

10.
11.
12.
9.120
9.121
9.122
9.123
9.124
9.125
9.126
9.127
9.128
9.129
9.130
9.131
9.132
9.133
9.134
10.1
11.1
11.2
12.1
12.2
SERIAL PERIPHERAL INTERFACE ...................................................................................... 126
FLOPPY DISK CONTROLLER ............................................................................................... 129
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
UART PORT ........................................................................................................................... 151
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.2.9
Using the SPI Interface via the LPC ................................................................................. 126
FDC Functional Description .............................................................................................. 129
Register Descriptions........................................................................................................ 140
Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................. 151
Register Description.......................................................................................................... 151
SYSFANIN SPEED LOW-BYTE VALUE (RPM) - Index 51h (Bank 6)....................... 120
CPUFANIN0 SPEED HIGH-BYTE VALUE (RPM) - Index 52h (Bank 6) ................... 120
CPUFANIN0 SPEED LOW-BYTE VALUE (RPM) - Index 53h (Bank 6) .................... 120
AUXFANIN0 SPEED HIGH-BYTE VALUE (RPM) - Index 54h (Bank 6).................... 121
AUXFANIN0 SPEED LOW-BYTE VALUE (RPM) - Index 55h (Bank 6) .................... 121
CPUFANIN1 SPEED HIGH-BYTE VALUE (RPM) - Index 56h (Bank 6) ................... 121
CPUFANIN1 SPEED LOW-BYTE VALUE (RPM) - Index 57h (Bank 6) .................... 122
AUXFANIN1 SPEED HIGH-BYTE VALUE (RPM) - Index 58h (Bank 6).................... 122
AUXFANIN1 SPEED LOW-BYTE VALUE (RPM) - Index 59h (Bank 6) .................... 122
FANOUT Configure register of PECI Error - Index 5Ah (Bank 6)............................... 123
FANCTRL2 pre-configured register for PECI error - Index 5Bh (Bank 6) .................. 123
FANCTRL3 pre-configured register for PECI error - Index 5Ch (Bank 6) .................. 123
FANCTRL4 pre-configured register for PECI error - Index 5Dh (Bank 6) .................. 124
FANCTRL5 pre-configured register for PECI error - Index 5Eh (Bank 6) .................. 124
FANCTRL6 pre-configured register for PECI error - Index 5Fh (Bank 6)................... 125
FIFO (Data) .............................................................................................................................129
Data Separator ........................................................................................................................130
Write Precompensation ...........................................................................................................130
Perpendicular Recording Mode ...............................................................................................130
FDC Core ................................................................................................................................131
FDC Commands ......................................................................................................................131
Status Register A (SA Register) (Read base address + 0)......................................................140
Status Register B (SB Register) (Read base address + 1)......................................................141
Digital Output Register (DO Register) (Write base address + 2) .............................................142
Tape Drive Register (TD Register) (Read base address + 3)..................................................143
Main Status Register (MS Register) (Read base address + 4) ................................................144
Data Rate Register (DR Register) (Write base address + 4) ...................................................144
FIFO Register (R/W base address + 5) ...................................................................................146
Digital Input Register (DI Register) (Read base address + 7)..................................................148
Configuration Control Register (CC Register) (Write base address + 7) .................................150
UART Control Register (UCR) (Read/Write)............................................................................151
UART Status Register (USR) (Read/Write) .............................................................................154
Handshake Control Register (HCR) (Read/Write) ...................................................................154
Handshake Status Register (HSR) (Read/Write).....................................................................155
UART FIFO Control Register (UFR) (Write only).....................................................................156
Interrupt Status Register (ISR) (Read only) .............................................................................156
Interrupt Control Register (ICR) (Read/Write)..........................................................................157
Programmable Baud Generator (BLL/BHL) (Read/Write)........................................................158
User-defined Register (UDR) (Read/Write) .............................................................................158
W83627DHG-P/W83627DHG-PT
-V-
Publication Release Date: July 09, 2009
Version 1.94