W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 32

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W83627DHG-PT

Manufacturer Part Number
W83627DHG-PT
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627DHG-PT

Pin Count
128
Lead Free Status / RoHS Status
Compliant

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Quantity
Price
Part Number:
W83627DHG-PT
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0
5.12.6 GPIO-6 Interface
See 5.4
5.12.7 GPIO-4 with WDTO# / SUSLED Multi-function
5.13 Particular ACPI Function pins
5.14 POWER PINS
VSBGATE#
FTPRST#
EN_ACPI
PWROK2
SYMBOL
SUSLED
SYMBOL
SUSLED
ATXPGD
SYMBOL
WDTO#
GPxx***
SUSC#
GPxx*
GP37
GP55
GP31
GP30
GP35
GP36
3VSB
Serial Port & Infrared Port Interface
PIN
---
---
PIN
64
70
91
92
87
69
PIN
61
I/OD
I/OD
OD
OD
I/O
12
12
12t
12t
I/OD
I/OD
I/OD
I/OD
I/OD
I/O
OD
IN
O
O
I/O
IN
IN
IN
12
12
cd
12t
12
t
t
t
+3.3 V stand-by power supply for the digital circuits.
12t
12t
12t
12
12
This GPxx* can serve as GPIO or the Watchdog Timer output
signals.
This GPxx*** can serve as GPIO or Suspend-LED output
signals.
SLP_S5# input.
General-purpose I/O port 3 bit 7
During VSB power reset (RSMRST#), this pin is pulled down
internally and is defined as EN_ACPI (enabling particular ACPI
functions), which provides the value for CR2C bit 4 (EN_ACPI).
The PCB layout should reserve space for a 1-kΩ resistor to pull
down this pin to ensure successful disabling of particular ACPI
functions, and a 1-kΩ resistor is recommended to pull the pin up
if wish to enable particular ACPI functions.
General-purpose I/O port 5 bit 5.
Suspended LED output.
Switch 3VSB power to memory when in S3 state. The default is
disabled while the particular ACPI functions are enabled. The
control bit is at Logical Device A, CR [E4h] bit 4.
General-purpose I/O port 3 bit 1.
This pin generates the PWROK2 signal while 3VCC comes in.
General-purpose I/O port 3 bit 0.
ATX power good input signal. It is connected to the PWROK
signal from the power supply for PWROK/PWROK2 generation.
The default is enabled.
General-purpose I/O port 3 bit 5.
Connect to the reset button. This pin has internal de-bounce
circuit whose de-bounce time is at least 32 mS.
General-purpose I/O port 3 bit 6.
W83627DHG-P/W83627DHG-PT
-22-
DESCRIPTION
DESCRIPTION
Publication Release Date: July 09, 2009
DESCRIPTION
Version 1.94

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