W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 164

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

12.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of data transfer during communication.
12.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls pins used with handshaking peripherals such as modems and also controls the
diagnostic mode of the UART.
DEFAULT
DEFAULT
BIT
NAME
NAME
7
6
5
4
3
2
1
0
BIT
BIT
RFEI. RX FIFO Error Indication. In 16450 mode, this bit is always set to logical 0. In
16550 mode, this bit is set to logical 1 when there is at least one parity-bit error and no
stop-bit error or silent-byte detected in the FIFO. In 16550 mode, this bit is cleared to
logical 0 by reading from the USR if there are no remaining errors left in the FIFO.
TSRE. Transmitter Shift Register Empty. In 16450 mode, this bit is set to logical 1
when TBR and TSR are both empty. In 16550 mode, it is set to logical 1 when the
transmit FIFO and TSR are both empty. Otherwise, this bit is set to logical 0.
TBRE. Transmitter Buffer Register Empty. In 16450 mode, when a data character is
transferred from TBR to TSR, this bit is set to logical 1. If ETREI or ICR is high, an
interrupt is generated to notify the CPU to write the next data. In 16550 mode, this bit is
set to logical 1 when the transmit FIFO is empty. It is set to logical 0 when the CPU writes
data into TBR or the FIFO.
SBD. Silent Byte Detected. This bit is set to logical 1 to indicate that received data are
kept in silent state for the time it takes to receive a full word, which includes the start bit,
data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the
data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0.
NSER. No Stop Bit Error. This bit is set to logical 1 to indicate that the received data
have no stop bit. In 16550 mode, it indicates the same condition for the data on the top of
the FIFO. When the CPU reads USR, it sets this bit to logical 0.
PBER. Parity Bit Error. This bit is set to logical 1 to indicate that the received data has
the wrong parity bit. In 16550 mode, it indicates the same condition for the data on the top
of the FIFO. When the CPU reads USR, it sets this bit to logical 0.
OER. Overrun Error. This bit is set to logical 1 to indicate that the received data have
been overwritten by the next received data before they are read by the CPU. In 16550
mode, it indicates the same condition, instead of FIFO full. When the CPU reads USR, it
sets this bit to logical 0.
RDR. RBR Data Ready. This bit is set to logical 1 to indicate that the received data are
ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or
FIFO, the bit is set to logical 0.
RFEI
7
0
7
0
RESERVED
TSRE
6
0
6
1
TBRE
5
0
5
1
W83627DHG-P/W83627DHG-PT
LOOPBACK
INTERNAL
ENABLE
DESCRIPTION
-154-
SBD
4
0
4
0
ENABLE
NSER
IRQ
3
0
3
0
Publication Release Date: July 09, 2009
LOOPBACK
RI INPUT
PBER
2
0
2
0
OER
RTS
1
0
1
0
Version 1.94
RDR
DTR
0
0
0
0