W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 136

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

10. SERIAL PERIPHERAL INTERFACE
The W83627DHG-P provides a bridge of the Low Pin Count (LPC) Interface to Serial Peripheral
Interface (SPI). The signals in the SPI are transmitted through Pin 2 (SCK), Pin 19 (SCE#), Pin 58 (SI),
and Pin 118 (SO). In the Super I/O (W83627DHG-P), these 4 pins are multi-functional. The SPI
functions are activated through strapping. Pin 52 determines whether to enable or disable the SPI
functions. In the Super I/O (W83627DHG-P), the SPI functions are activated when Pin 52 is pulled-up
to the power source. The function status can be seen/read at CR [24h], bit 1.
The SPI is primarily used to store the BIOS ROM. When booting the computer, the memory read
instructions or timing sequences are transmitted from the CPU, the South Bridge, the LPC bus to the
Super I/O (W83627DHG-P). After receiving the instruction, the Super I/O (W83627DHG-P) generates
and transmits the correct instructions and memory addresses to the SPI which responds with the
corresponding data of the addresses. The data are placed to the LPC bus by the Super I/O
(W83627DHG-P) and returned to the South Bridge. All of the data are read in this manner. By setting
the registers shown at Table 10.3, the Super I/O (W83627DHG-P) supports all the instructions given,
such as erase, read, program, to SPI flash. For more details, please see
To make it more user-friendly, regularly used SPI instructions/functions can be generated via the LPC
I/O read/write commands. That is, the flash devices with SPI can be programmed, erased, or read on
the motherboard.
10.1 Using the SPI Interface via the LPC
LOGICAL DEVICE
The functions and definitions of the 8 bytes are shown in the following table.
Address
Base+0
6
The allowed range is 8 bytes above the base address. The base address is configured at
Configuration Register CR62h and CR63h in Logical Device 6. For example, if 03h is
written to Configuration Register CR62h, and F8h to Configuration Register CR63h,
03F8h ~ 03FFh is the allowed range.
Functions and Definitions
Bit
7:0
7:4
CONFIGURATION
REGISTER
Table 10-1 Base Address Setting
Function
62
63
MODE
Table 10-2 SPI Address Map
CMD
W83627DHG-P/W83627DHG-PT
-126-
Mode execution. Please see
Commands or instructions of each SPI device
BIT
7:0
7:0
the details of each mode.
Publication Release Date: July 09, 2009
High byte of Base Address
Low byte of Base Address
Description
Table 10-2 SPI Address
FUNCTION
Table 10-3 MODE
Version 1.94
Map.
for