W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 199

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

18. GENERAL PURPOSE I/O
The W83627DHG-P provides 40 input/output ports that can be individually configured to perform a
simple basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control
registers in Logical Device 7, and GPIO ports 2 ~ 5 in Logical Device 9. Users can configure each
individual port to be an input or output port by programming respective bit in selection register (0 =
output, 1 = input). Invert port value by setting inversion register (0 = non -inverse, 1 = inverse). Port
value is read / written through data register.
In addition, only GP30, GP31 and GP35 are designed to be able to assert PSOUT# or PME# signal to
wake up the system if any of them has any transitions. There are about 16mS debounced circuit inside
these 3 GPIOs and it can be disabled by programming respective bit (LD9, CR [FEh] bit 4~6). Users
can set what kind of event type, level or edge, and polarity, rising or falling, to perform the wake-up
function. The following table gives a more detailed register map on GP30, GP31 and GP35.
GP30
GP31
GP35
LDA,
CR[FEh]
bit4
LDA,
CR[FEh]
bit5
LDA,
CR[FEh]
bit6
EVENTROUTE
0: DISABLE
1: ENABLE
(PSOUT#)
I
LDA,
CR[FEh]
bit0
LDA,
CR[FEh]
bit1
LDA,
CR[FEh]
bit2
EVENTROUTE
0: DISABLE
1: ENABLE
(PME#)
II
W83627DHG-P/W83627DHG-PT
LD9,
CR[FEh]
bit4
LD9,
CR[FEh]
bit5
LD9,
CR[FEh]
bit6
DEBOUNCED
1 : DISABLE
0 : ENABLE
EVENT
-189-
1: LEVEL
LD9,
CR[FEh]
bit0
LD9,
CR[FEh]
bit1
LD9,
CR[FEh]
bit2
0 : EDGE
EVENT
TYPE
Publication Release Date: July 09, 2009
0 : RISING
LD9,
CR[F2h]
bit0
LD9,
CR[F2h]
bit1
LD9,
CR[F2h]
bit5
1 : FALLING
POLARITY
EVENT
LD9,
CR[E7h]
bit0
LD9,
CR[E7h]
bit1
LD9,
CR[E7h]
bit5
Version 1.94
STATUS
EVENT