W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 192

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by
programming Logical Device A, CR [E6h], bit 3 to “1”. Furthermore, the W83627DHG-P provides four
different extra delay time of PWROK for various demands. The four extra delay time are designed at
Logical Device A, CR [E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR [E6h] bits 3 ~1.
For example, if Logical Device A, CR [E6h] bit 3 is set to “0” and bits 2~1 are set to “10”, the range of
t2 timing is from 396 (300 + 96) mS to 596 (500 + 96) mS.
15.4.1
PWROK and PWROK2 signals as well as ATXPGD and FTPRST# input signals are interrelated.
Once the FTPRST# signal changes from high to low then to high, the PWROK and PWROK2 signals
will have the same transition after 28mS ~ 39mS delay.
following figure and table.
SYMBOL
V3
V4
t2
LOGICAL DEVICE A,
CR[E6H] BIT[3:1]
The Relation among PWROK/PWROK2, ATXPGD and FTPRST#
3VCC Valid Voltage
3VCC Ineffective Voltage
Valid 3VCC to PWROK active
2~1
3
Table 15-5 Bit Map of Logical Device A, CR [E6h], Bits [3:1]
PARAMETER
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
10: 96 mS
W83627DHG-P/W83627DHG-PT
Table 15-4
-182-
The relation and parameter are illustrated in the
DEFINITION
MIN.
2.25
300
2.4
01: Delay 32 mS
11: Delay 250 mS
Publication Release Date: July 09, 2009
TYP.
2.6
2.4
-
MAX.
2.75
2.55
500
Version 1.94
UNIT
mS
V
V