W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 167

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
12.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register enables and disables the five types of controller interrupts separately. A selected
interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally
disabled by setting bits 0 through 3 to logical 0.
DEFAULT
Bit
3
0
0
0
1
0
0
BIT
BIT
7-4
NAME
3
2
1
0
3
2
1
0
BIT
Bit
2
0
1
1
1
0
0
ISR
INTERRUPT STATUS BIT2. In 16450 mode, this bit is logical 0. In 16550 mode, bit 3 and
2 are set to logical 1 when a time-out interrupts is pending. See the table below.
INTERRUPT STATUS BIT1.
INTERRUPT STATUS BIT0.
0 IF INTERRUPT PENDING. This bit is logical 1 if there is no interrupt pending. If one of
the interrupt sources has occurred, this bit is set to logical 0.
RESERVED. These four bits are always logical 0.
EHSRI. Set this bit to logical 1 to enable the handshake status register interrupt.
EUSRI. Set this bit to logical 1 to enable the UART status register interrupt.
ETBREI. Set this bit to logical 1 to enable the TBR empty interrupt.
ERDRI. Set this bit to logical 1 to enable the RBR data ready interrupt.
Bit
1
0
1
0
0
1
0
Bit
0
1
0
0
0
0
0
7
0
Interrupt
priority
First
Second
Second
Third
Fourth
-
6
0
RESERVED
Interrupt Type
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
TBR Empty
Handshake status
-
5
0
W83627DHG-P/W83627DHG-PT
INTERRUPT SET AND FUNCTION
DESCRIPTION
DESCRIPTION
-157-
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
4
0
reached
These two bits identify the priority level of
the pending interrupt, as shown in the table
below.
EHSRI
2. PBER =1
4. TDCD = 1
2. TDSR = 1
3
0
Publication Release Date: July 09, 2009
EUSRI
2
0
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
Read HSR
ETBREI
third)
1
0
-
Version 1.94
ERDRI
0
0