W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 184

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

14.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is
controlled by LD5-CRF0 as follows:
14.5.1 KB Control Register
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATEA20 according to received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the
KBRESET is pulse low for 6μs (Min.) with a 14μs (Min.) delay.
GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually
exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set.
DEFAULT
NAME
BIT
5-3
BIT
7
6
2
1
0
KCLKS1
KCLKS0
RESERVED.
P92EN. Port 92 Enable.
1: Enable Port 92 to control GATEA20 and KBRESET.
0: Disable Port 92 functions.
HGA20. Hardware GATEA20.
1: Selects hardware GATEA20 control logic to control GATE A20 signal.
0: Disable hardware GATEA20 control logic function.
HKBRST#. Hardware Keyboard Reset.
1: Select hardware KB RESET control logic to control KBRESET signal.
0: Disable hardware KB RESET control logic function.
KCLKS1
7
1
KCLKS0
6
0
0
5
W83627DHG-P/W83627DHG-PT
Reserved
DESCRIPTION
-174-
0
4
These two bits select the KBC clock rate.
Bits
7 6
0 0: Reserved.
0 1: Reserved.
1 0: KBC clock input is 12 MHz.
1 1: Reserved.
3
0
Publication Release Date: July 09, 2009
P92EN
2
0
HGA20
0
1
Version 1.94
HKBRST#
0
0