W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 232

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CR E6h. (Default 1Ch)
3~1
BIT READ / WRITE
BIT
7
6
5
4
0
1
0
Reserved.
R / W-Clear
READ / WRITE
R / W
R / W
R / W
R / W
R / W
R / W
ENMDAT => (VSB)
Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY,
CRE0[1]) define the combinations of the mouse wake-up events. Please
see the table in CRE0, bit 4 for the details.
CASEOPEN Clear Control. (VSB)
Write 1 to this bit to clear CASEOPEN status. This bit will not clear the
status itself. Please write 0 after an event is cleared. The function is the
same as Index 46h bit 7 of H/W Monitor part.
Power-loss Last State Flag. (VBAT)
0: ON
1: OFF.
PWROK_DEL (VSB)
Set the delay time when rising from 3VCC to PWROK
Bits
3 2 1
0 0 0: 300 ~ 600mS
0 0 1: 330 ~ 670mS
0 1 0: 390 ~ 730mS
0 1 1: 520 ~ 860mS
1 0 0: 200 ~ 300mS
1 0 1: 230 ~ 370mS
1 1 0: 290 ~ 430mS
1 1 1: 420 ~ 560mS
PWROK_TRIG =>
Write 1 to re-trigger the PWROK signal from low to high.
PWROK source selection.
0: PSON#
1: SUSB#
ATXPGD signal to control PWROK and PWROK2 generation
0: Enable.
1: Disable.
W83627DHG-P/W83627DHG-PT
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DESCRIPTION
DESCRIPTION
Publication Release Date: July 09, 2009
Version 1.94