W83627DHG-PT Nuvoton Technology Corporation of America, W83627DHG-PT Datasheet - Page 154

• Manufacturer Part Number: W83627DHG-PT
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG-PT

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

11.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
11.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-
AT and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR
register. As a result, the real data rate is determined by the most recent write to either the DR or CC
register. The bit definitions for this register are as follows:
DEFAULT
DEFAULT
NAME
NAME
BIT
3-1
BIT
7
6
5
4
0
7
6
5
4
BIT
BIT
TAPE SEL 1
RQM. Request for Master. A high on this bit indicates Data Register is ready to send or
receive data to or from the processor.
DIO. Data Input/Output. If DIO= HIGH, the transfer is from Data Register to the
processor. If DIO=LOW, the transfer is from the processor to Data Register.
NON-DMA MODE. The FDC is in the non-DMA mode. This bit is set only during the
execution phase in the non-DMA mode. Transition to LOW state indicates execution
phase has ended.
CB. FDC Busy. A read or write command is in the process when CB = HIGH.
RESERVED.
FDD0 BUSY. (D0B = 1). FDD number 0 is in the SEEK mode.
S/W RESET. This bit is the software reset bit.
POWER DOWN.
0: The FDC is in the normal mode.
1: The FDC is in the power-down mode.
RESERVED.
PRECOMP 2.
1
1
RESET
S/W
RQM
7
0
7
0
POWER
DOWN
6
0
DIO
NA
6
RESERVED
NON-DMA
TAPE SEL 0
MODE
5
0
NA
5
W83627DHG-P/W83627DHG-PT
0
1
PRECOMP
DESCRIPTION
DESCRIPTION
-144-
NA
CB
4
0
2
4
These three bits select the value of write
PRECOMP
NA
3
3
1
0
Publication Release Date: July 09, 2009
RESERVED
DRIVE SELECTED
PRECOMP
NA
2
2
0
0
2
3
DRATE 1
NA
1
1
1
Version 1.94
DRATE 0
FDD 0
BUSY
NA
0
0
0