s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 157

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

SFTRES — Soft Reset
12.13.2 MSCAN08 Module Control Register 1
LOOPB — Loop Back Self-Test Mode
WUPM — Wakeup Mode
Freescale Semiconductor
When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing
transmission or reception is aborted and synchronization to the bus is lost.
The following registers enter and stay in their hard reset state:
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR3, and CIDMR0–CIDMR3 can only
be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are
not affected by soft reset.
When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the
MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions.
When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test
operation: the bit stream output of the transmitter is fed back to the receiver internally. The CAN
input pin is ignored and the CAN
it does normally when transmitting and treats its own transmitted message as a message received
from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN
frame Acknowledge field to insure proper reception of its own message. Both transmit and receive
interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from
spurious wakeups (see
1 = MSCAN08 in soft reset state
0 = Normal operation
1 = Activate loop back self-test mode
0 = Normal operation
1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length
0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus.
CMCR0, CRFLG, CRIER, CTFLG, and CTCR.
of at least t
Address:
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
wup
$0501
Bit 7
.
0
0
Figure 12-17. Module Control Register (CMCR1)
12.8.5 Programmable Wakeup
= Unimplemented
6
0
0
TX
output goes to the recessive state (1). The MSCAN08 behaves as
5
0
0
4
0
0
Function).
3
0
0
Programmer’s Model of Control Registers
LOOPB
2
0
WUPM
1
0
CLKSRC
Bit 0
0
RX
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