s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 310

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

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20.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
20.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
20.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V
on IRQ and the reset vector blank, then the baud rate is independent of PTB4.
Table 20-1
effective baud rate is the bus frequency divided by 278. If using a crystal as the clock source, be aware
of the upper frequency limit that the internal clock module can handle. See
or
20.3.1.7 Commands
The monitor ROM firmware uses these commands:
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
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21.8 3.3-Volt Control Timing
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
also lists external frequencies required to achieve a standard baud rate of 7200 bps. The
Wait one bit time after each echo before sending the next byte.
START
BIT
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
0
BIT 0
1
2
BIT 1
TST
for this limit.
MISSING STOP BIT
3
Figure 20-12. Monitor Data Format
) upon entry into monitor mode. If monitor mode was entered with V
Figure 20-13. Break Transaction
4
BIT 2
5
6
BIT 3
7
BIT 4
NOTE
BIT 5
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
BIT 6
0
1
BIT 7
2
3
STOP
BIT
4
21.7 5.0-Volt Control Timing
START
NEXT
5
BIT
6
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