s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 221

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s908gz60cfa

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s908gz60cfa
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit
(CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in
Figure
controller that coordinates CPU and exception timing.
The SIM is responsible for:
Table 15-1
Freescale Semiconductor
Bus clock generation and control for CPU and peripherals:
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt arbitration
15-1.
Stop/wait/reset/break entry and recovery
Internal clock control
shows the internal signal names used in this section.
Table 15-1
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
PORRST
IRST
R/W
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
IAB
IDB
is a summary of the SIM input/output (I/O) registers. The SIM is a system state
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 15-1. Signal Name Conventions
Description
221

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