s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 161

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

TERRIF — Transmitter Error Passive Interrupt Flag
BOFFIF — Bus-Off Interrupt Flag
OVRIF — Overrun Interrupt Flag
RXF — Receive Buffer Full
1. Condition to set the flag: TERRIF = (128 → TEC → 255) & BOFFIF
Freescale Semiconductor
This flag is set when the MSCAN08 goes into error passive status due to the transmit error counter
exceeding 127 and the bus-off interrupt flag is not set
while this flag is set.
This flag is set when the MSCAN08 goes into bus-off status, due to the transmit error counter
exceeding 255. It cannot be cleared before the MSCAN08 has monitored 128 times 11 consecutive
‘recessive’ bits on the bus. If not masked, an error interrupt is pending while this flag is set.
This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while
this flag is set.
The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive
buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the
CPU has read that message from the receive buffer the RXF flag must be cleared to release the buffer.
A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. If
not masked, a receive interrupt is pending while this flag is set.
1 = MSCAN08 went into transmit error passive status.
0 = No transmit error passive status has been reached.
1 = MSCAN08has gone into bus-off status.
0 = No bus-off status has been reached.
1 = A data overrun has been detected since last clearing the flag.
0 = No data overrun has occurred.
1 = The receive buffer is full. A new message is available.
0 = The receive buffer is released (not full).
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
NOTE
(1)
. If not masked, an error interrupt is pending
Programmer’s Model of Control Registers
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