s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 276

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM1)
TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
18.8.5 TIM1 Channel Registers
These read/write registers contain the captured TIM1 counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM1 channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM1 channel x registers
(T1CHxH) inhibits input captures until the low byte (T1CHxL) is read.
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When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin.
the ELSxB and ELSxA bits.
When channel x is an output compare channel, this read/write bit controls the behavior of the channel x
output when the TIM1 counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
1 = Channel x pin toggles on TIM1 counter overflow.
0 = Channel x pin does not toggle on TIM1 counter overflow.
After initially enabling a TIM1 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
When TOVx is set, a TIM1 counter overflow takes precedence over a
channel x output compare if both occur at the same time.
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
CHxMAX
TCHx
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
OVERFLOW
COMPARE
Figure 18-9
PERIOD
OUTPUT
OVERFLOW
Figure 18-9. CHxMAX Latency
shows, the CHxMAX bit takes effect in the cycle after it is set
Table 18-2
COMPARE
OUTPUT
NOTE
NOTE
NOTE
OVERFLOW
shows how ELSxB and ELSxA work. Reset clears
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
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