s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 163

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.13.7 MSCAN08 Transmitter Flag Register
The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A
flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag
setting. The transmitter buffer empty flags each have an associated interrupt enable bit in the CTCR
register. A hard or soft reset will resets the register.
ABTAK2–ABTAK0 — Abort Acknowledge
TXE2–TXE0 — Transmitter Empty
Freescale Semiconductor
This flag acknowledges that a message has been aborted due to a pending abort request from the
CPU. After a particular message buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been aborted successfully or has been sent.
The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is cleared.
This flag indicates that the associated transmit message buffer is empty, thus not scheduled for
transmission. The CPU must handshake (clear) the flag after a message has been set up in the
transmit buffer and is due for transmission. The MSCAN08 sets the flag after the message has been
sent successfully. The flag is also set by the MSCAN08 when the transmission request was
successfully aborted due to a pending abort request (see
If not masked, a receive interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag (ABTAK, see above). When a TXEx
flag is set, the corresponding ABTRQx bit (ABTRQ) is cleared. See
Control Register
1 = The message has been aborted.
0 = The message has not been aborted, thus has been sent out.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message due for transmission).
Address:
To ensure data integrity, no registers of the transmit buffers should be
written to while the associated TXE flag is cleared.
The CTFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$0506
Bit 7
0
0
Figure 12-22. Transmitter Flag Register (CTFLG)
= Unimplemented
ABTAK2
5
6
0
ABTAK1
5
0
NOTE
ABTAK0
4
0
3
0
0
12.12.5 Transmit Buffer Priority
Programmer’s Model of Control Registers
TXE2
2
1
12.13.8 MSCAN08 Transmitter
TXE1
1
1
TXE0
Bit 0
1
Registers).
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