s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 294

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM2)
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
294
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM2 counter registers matches the value in the TIM2 channel x registers.
When CHxIE = 1, clear CHxF by reading TIM2 channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM2 CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Address: $0033
Address: $0456
Address: $0459
Address: $045C
Address: $045F
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Figure 19-8. TIM2 Channel Status and Control Registers
CH1F
CH2F
CH3F
CH4F
CH5F
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
T2SC1
T2SC2
T2SC3
T2SC4
T2SC5
= Unimplemented
CH1IE
CH2IE
CH3IE
CH4IE
CH5IE
6
0
6
0
6
0
6
0
6
0
(T2SC0:T2SC5) (Continued)
MS2B
MS4B
5
0
0
5
0
5
0
0
5
0
5
0
0
MS1A
MS2A
MS3A
MS4A
MS5A
4
0
4
0
4
0
4
0
4
0
ELS1B
ELS2B
ELS3B
ELS4B
ELS5B
3
0
3
0
3
0
3
0
3
0
ELS1A
ELS2A
ELS3A
ELS4A
ELS5A
2
0
2
0
2
0
2
0
2
0
TOV1
TOV2
TOV3
TOV4
TOV5
1
0
1
0
1
0
1
0
1
0
Freescale Semiconductor
CH2MAX
CH4MAX
CH1MAX
CH3MAX
CH5MAX
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
0