s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 237

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.7.1 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
15.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V
other bits are set.
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
Freescale Semiconductor
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
1 = Last reset caused by POR circuit
0 = Read of SRSR
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
1 = Last reset caused by COP counter
0 = POR or read of SRSR
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$FE00
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POR
Bit 7
Bit 7
R
R
0
1
Figure 15-22. SIM Reset Status Register (SRSR)
Figure 15-21. Break Status Register (BSR)
= Unimplemented
= Reserved
PIN
R
6
0
6
0
IH
at this time, then the PIN bit may be set, in addition to whatever
COP
R
5
0
5
0
1. Writing a 0 clears SBSW.
ILOP
R
4
0
4
0
ILAD
R
3
0
3
0
MODRST
R
2
0
2
0
Note
SBSW
LVI
1
0
1
0
(1)
Bit 0
Bit 0
R
0
0
0
SIM Registers
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