s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 93

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

OSCENINSTOP — Oscillator Enable In Stop Mode Bit
SCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
Freescale Semiconductor
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module
the rest of the MCU stops. See
cease to generate clocks while in stop mode. The default state for this option is clear, disabling the
oscillator in stop mode.
SCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See
Communications Interface (ESCI)
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module.
See
LVIPWRD disables the LVI module. See
1 = Oscillator enabled during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal data bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
Chapter 11 Low-Voltage Inhibit
Note: LVI5OR3 is only reset via POR (power-on reset).
Address:
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
Chapter 17 Timebase Module
Module.
(CGM). This function is used to keep the timebase running while
(LVI).
LVIRSTD
5
0
Chapter 11 Low-Voltage Inhibit
LVIPWRD
4
0
LVI5OR3
See note
3
(TBM). When clear, the oscillator will
Chapter 14 Enhanced Serial
SSREC
2
0
Chapter 6 Computer Operating
(LVI).
STOP
1
0
Functional Description
COPD
Bit 0
0
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