s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 229

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
Freescale Semiconductor
INTERRUPT
I BIT
INTERRUPT
R/W
I BIT
IDB
R/W
IAB
IDB
IAB
MODULE
MODULE
Figure 15-11
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
DUMMY
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
DUMMY
SP – 4
SP
demonstrates what happens when two interrupts are pending. If an interrupt
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 15-9. Interrupt Recovery Timing
Figure 15-8
SP – 3
SP – 1
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
X
NOTE
SP – 1
SP – 3
PC – 1 [7:0] PC – 1 [15:8] OPCODE
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
PC + 1
VECT L
OPERAND
V DATA L
START ADDR
OPCODE
Exception Control
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