s908gz60cfa Freescale Semiconductor, Inc, s908gz60cfa Datasheet - Page 82

• Manufacturer Part Number: s908gz60cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
directly from the crystal oscillator circuit.
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-3
82
Addr.
$0036
$0037
$0038
•
•
•
•
•
PLL control register (PCTL)
(See
PLL bandwidth control register (PBWC)
(See
PLL multiplier select register high (PMSH)
(See
PLL multiplier select register low (PMSL)
(See
PLL VCO range select register (PMRS)
(See
PLL Multiplier Select High
is a summary of the CGM registers.
PLL Bandwidth Control
Register Name
4.5.1 PLL Control
4.5.2 PLL Bandwidth Control
4.5.3 PLL Multiplier Select Register
4.5.4 PLL Multiplier Select Register
4.5.5 PLL VCO Range Select
PLL Control Register
Register (PBWC)
Register (PMSH)
See page 83.
See page 85.
See page 86.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
(PCTL)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Register.)
Figure 4-3. CGM I/O Register Summary
PLLIE
AUTO
Bit 7
0
0
0
0
Figure 4-2
Register.)
= Unimplemented
Register.)
LOCK
PLLF
6
0
0
0
0
High.)
Low.)
shows only the logical relation of CGMXCLK to OSC1
PLLON
ACQ
5
1
0
0
0
BCS
R
4
0
0
0
0
0
= Reserved
MUL11
R
3
0
0
0
0
MUL10
R
2
0
0
0
0
Freescale Semiconductor
XCLK
VPR1
MUL9
1
0
0
0
0
) and comes
VPR0
MUL8
Bit 0
R
0
0
0