C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet
C8051F060_07
Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.C8051F060_07.pdf
(328 pages)
Preliminary Rev. 1.2 7/04
Analog Peripherals
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On-Chip JTAG Debug & Boundary Scan
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Two 16-Bit SAR ADCs
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10-bit SAR ADC (C8051F060/1/2/3)
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Two 12-bit DACs (C8051F060/1/2/3)
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Three Analog Comparators
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Voltage Reference
Precision VDD Monitor/Brown-Out Detector
On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
16-bit resolution
±0.75 LSB INL, guaranteed no missing codes
Programmable throughput up to 1 Msps
Operate as two single-ended or one differential con-
verter
Direct memory access; data stored in RAM without
software overhead
Data-dependent windowed interrupt generator
Programmable throughput up to 200 ksps
8 external inputs, single-ended or differential
Built-in temperature sensor
Can synchronize outputs to timers for jitter-free wave-
form generation
Programmable hysteresis/response time
INTERRUPTS
ANALOG PERIPHERALS
C8051F060/1/2/3 Only
1 Msps
1 Msps
Copyright © 2004 by Silicon Laboratories
8051 CPU
(25MIPS)
16-bit
16-bit
200ksps
ADC
ADC
22
10-bit
HIGH-SPEED CONTROLLER CORE
ADC
VREF
SENSOR
TEMP
Interface
CIRCUITRY
DMA
COMPARATOR
DEBUG
+
-
ISP FLASH
VOLTAGE
64/32 kB
+
-
S
+
-
12-Bit
12-Bit
DAC
DAC
Mixed Signal ISP Flash MCU Family
High Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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Supply Voltage .......................... 2.7 to 3.6 V
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100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
C8051F060/1/2/3/4/5/6/7
CIRCUIT
CLOCK
SPI Bus
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
C8051F060/1/2/3
UART0
UART1
SMBus
CAN 2.0B
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Flexible Interrupt sources
4352 Bytes internal data RAM (4 k + 256)
64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
Flash; In-system programmable in 512-byte sectors
External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
59 general purpose I/O pins (C8051F060/2/4/6)
24 general purpose I/O pins (C8051F061/3/5/7)
Bosch Controller Area Network (CAN 2.0B -
C8051F060/1/2/3)
Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
Internal calibrated precision oscillator: 24.5 MHz
External oscillator: Crystal, RC, C, or clock
Multiple power saving sleep and shutdown modes
PCA
4352 B
SRAM
DIGITAL I/O
100 pin Only
CONTROL
SANITY
JTAG
Port 3
Port 4
Port 5
Port 6
Port 7
Port 0
Port 1
Port 2
C8051F060/1/2/3/4/5/6/7
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