C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 78

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
6.5.
When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW,
Figure 6.9) is loaded with the address contained within the DMA Instruction Boundary Register
(DMA0BND, Figure 6.8). The instruction is fetched from the Instruction Buffer, and the DMA Control Logic
waits for data from the appropriate ADC(s). At the end of an instruction, the Repeat Counter (Registers
DMA0CSH and DMA0CSL) is decremented, and the instruction will be repeated until the Repeat Counter
reaches 0x0000. The Repeat Counter is then reset to the Repeat Counter Limit value (Registers
DMA0CTH and DMA0CTL), and the DMA will increment DMA0ISW to the next instruction address. When
the current DMA instruction is an End of Operation instruction, the Instruction Status Register is reset to
the Instruction Boundary Register. If the Continuous Conversion bit (bit 7, CCNV) in the End of Operation
instruction word is set to ‘1’, the DMA will continue to execute instructions. When CCNV is set to ‘0’, the
DMA will stop executing instructions at this point. An example of Mode 1 operation is shown in Figure 6.3.
78
DMA0BND
Instruction Execution in Mode 1
0x3F
0x03
0x02
0x01
0x00
...
INSTRUCTION
(64 Bytes)
BUFFER
00000000
00110000
01000000
00010000
Figure 6.3. DMA Mode 1 Operation
Rev. 1.2
ADC0H (Diff.)
ADC0H (Diff.)
ADC0L (Diff.)
ADC0L (Diff.)
ADC1H
ADC0H
ADC1H
ADC0H
ADC0H
ADC0H
ADC0H
ADC1L
ADC0L
ADC1L
ADC0L
ADC0L
ADC0L
ADC0L
XRAM
DMA0CSH:L = 0x0000
DMA0CSH:L = DMA0CTH:L
DMA0CSH:L = 0x0000
DMA0CSH:L = DMA0CTH:L
DMA0CSH:L = 0x0000
DMA0CSH:L = DMA0CTH:L - 1
DMA0CSH:L = DMA0CTH:L