C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 218

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
218
Bits7-0:
Note:
Bits7-0:
P3.7
R/W
R/W
Bit7
Bit7
P3.[7:0]: Port3 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.
Although P3 is not brought out to pins on the C8051F061/3/5/7 devices, the Port Data regis-
ter is still present and can be used by software. See “Configuring Ports which are not Pinned
Out” on page 219.
P3MDOUT.[7:0]: Port3 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
P3.6
R/W
R/W
Bit6
Bit6
Figure 18.18. P3MDOUT: Port3 Output Mode Register
P3.5
R/W
R/W
Bit5
Bit5
Figure 18.17. P3: Port3 Data Register
P3.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P3.3
R/W
R/W
Bit3
Bit3
P3.2
R/W
R/W
Bit2
Bit2
P3.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P3.0
R/W
R/W
Bit0
Bit0
0xB0
All Pages
0xA7
F
Addressable
Reset Value
Reset Value
00000000
11111111
Bit