C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 202

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
C8051F060/1/2/3/4/5/6/7
202
Parameter
T
T
T
T
T
T
T
T
T
T
ACS
ACW
ACH
ALEH
ALEL
SYSCLK
WDS
WDH
RDS
RDH
Description
System Clock Period
Address / Control Setup Time
Address / Control Pulse Width
Address / Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
Write Data Hold Time
Read Data Setup Time
Read Data Hold Time
Table 17.1. AC Parameters for External Memory Interface
Rev. 1.2
1*T
1*T
1*T
1*T
Min
SYSCLK
SYSCLK
SYSCLK
SYSCLK
40
20
0
0
0
0
16*T
19*T
3*T
3*T
4*T
4*T
3*T
Max
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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