C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 244

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
20.4.2. Clock Rate Register
244
Bits7-0:
R/W
Bit7
SMB0CR.[7:0]: SMBus0 Clock Rate Preset.
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master
mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The
timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation , where SMB0CR is the
unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz:
The resulting SCL signal high and low times are given by the following equations:
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the
following equation:
R/W
Bit6
SMB0CR
Figure 20.9. SMB0CR: SMBus0 Clock Rate Register
T
R/W
Bit5
T
HIGH
BFT
<
T
( (
LOW
≅
288
≅
10
(
258 SMB0CR
=
R/W
Bit4
–
×
(
0.85
(
---------------------------------------------------- -
256 SMB0CR
–
256 SMB0CR
⋅
–
–
SYSCLK )
Rev. 1.2
SYSCLK
R/W
Bit3
) SYSCLK
⁄
) SYSCLK
⁄
)
(
⁄
R/W
Bit2
1.125 10
+
1
+
⋅
625ns
R/W
Bit1
6
) )
SFR Address:
SFR Page:
R/W
Bit0
0xCF
0
Reset Value
00000000