C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 274

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
274
Bits7-6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM00
R/W
Bit7
SM00-SM10: Serial Port Operation Mode:
Write:
When written, these bits select the Serial Port Operation Mode as follows:
Reading these bits returns the current UART0 mode as defined above.
SM20: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
Mode 2 and 3: Multiprocessor Communications Enable.
received address matches the UART0 address or the broadcast address.
REN0: Receive Enable.
This bit enables/disables the UART0 receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is
not used in Modes 0 and 1. Set or cleared by software as required.
RB80: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM20 is logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in
Mode 0, or at the beginning of the stop bit in other modes). When the UART0 interrupt is
enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine.
This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART0 (as selected by the
SM20 bit). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to
the UART0 interrupt service routine. This bit must be cleared manually by software.
SM00
SM10
R/W
Bit6
0
0
1
1
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the
SM10
SM20
0
1
0
1
R/W
Bit5
Figure 22.8. SCON0: UART0 Control Register
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
REN0
Mode 2: 9-Bit UART, Fixed Baud Rate
R/W
Bit4
Mode 0: Synchronous Mode
TB80
R/W
Bit3
Rev. 1.2
Mode
RB80
R/W
Bit2
R/W
Bit1
TI0
SFR Address:
SFR Page:
R/W
RI0
Bit0
0x98
0
Addressable
Reset Value
00000000
Bit