C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 294

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
C8051F060/1/2/3/4/5/6/7
294
Bits 7-0: TL0: Timer 0 Low Byte.
Bits 7-0: TL1: Timer 1 Low Byte.
Bits 7-0: TH0: Timer 0 High Byte.
Bits 7-0: TH1: Timer 1 High Byte.
R/W
R/W
R/W
R/W
Bit7
Bit7
Bit7
Bit7
The TL0 register is the low byte of the 16-bit Timer 0
The TL1 register is the low byte of the 16-bit Timer 1.
The TH0 register is the high byte of the 16-bit Timer 0.
The TH1 register is the high byte of the 16-bit Timer 1.
R/W
R/W
R/W
R/W
Bit6
Bit6
Bit6
Bit6
R/W
R/W
R/W
R/W
Bit5
Bit5
Bit5
Bit5
Figure 24.10. TH1: Timer 1 High Byte
Figure 24.9. TH0: Timer 0 High Byte
Figure 24.7. TL0: Timer 0 Low Byte
Figure 24.8. TL1: Timer 1 Low Byte
R/W
R/W
R/W
R/W
Bit4
Bit4
Bit4
Bit4
Rev. 1.2
R/W
R/W
R/W
R/W
Bit3
Bit3
Bit3
Bit3
R/W
R/W
R/W
R/W
Bit2
Bit2
Bit2
Bit2
R/W
R/W
R/W
R/W
Bit1
Bit1
Bit1
Bit1
SFR Address:
SFR Address:
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SFR Page:
SFR Page:
R/W
R/W
R/W
Bit0
R/W
Bit0
Bit0
Bit0
0x8A
0
0x8B
0
0x8D
0
0x8C
0
Reset Value
Reset Value
Reset Value
00000000
00000000
Reset Value
00000000
00000000

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