C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 60

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
60
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select.
Bit 1:
Bit 0:
AD0EN
R/W
Bit7
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions or calibrations.
AD0TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by AD0CM1-0 bits.
AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.
AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM1-0 = 00b.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR0.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion.
01: Tracking started by the overflow of Timer 3 and is followed by the conversion.
10: ADC0 conversion starts on rising CNVSTR0 edge.
11: Tracking started by the overflow of Timer 2 and is followed by the conversion.
See Figure 5.4 and Table 5.1 for conversion timing parameters.
AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
RESERVED: Write to 0b.
AD0TM
R/W
Bit6
AD0INT AD0BUSY
R/W
Bit5
Figure 5.9. ADC0CN: ADC0 Control Register
R/W
Bit4
AD0CM1
Rev. 1.2
R/W
Bit3
AD0CM0
R/W
Bit2
AD0WINT
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
-
0xE8
0
Bit Addressable
Reset Value
00000000