C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 61
C8051F060_07
Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.C8051F060_07.pdf
(328 pages)
- Current page: 61 of 328
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Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3-1: AD1CM2-0: ADC1 Start of Conversion Mode Select.
Bit 0:
AD1EN
R/W
Bit7
AD1EN: ADC1 Enable Bit.
0: ADC1 Disabled. ADC1 is in low-power shutdown.
1: ADC1 Enabled. ADC1 is active and ready for data conversions or calibrations.
AD1TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by AD1CM2-0 bits.
AD1INT: ADC1 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC1 has not completed a data conversion since the last time this flag was cleared.
1: ADC1 has completed a data conversion.
AD1BUSY: ADC1 Busy Bit.
Read:
0: ADC1 Conversion is complete or a conversion is not currently in progress. AD1INT is set
to logic 1 on the falling edge of AD1BUSY.
1: ADC1 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC1 Conversion if AD1CM2-0 = 000b.
If AD1TM = 0:
000: ADC1 conversion initiated on every write of ‘1’ to AD1BUSY.
010: ADC1 conversion initiated on overflow of Timer 3.
100: ADC1 conversion initiated on rising edge of external CNVSTR1.
110: ADC1 conversion initiated on overflow of Timer 2.
xx1: ADC1 conversion initiated on every write of ‘1’ to AD0BUSY in ADC0CN
If AD1TM = 1:
000: Tracking starts with the write of ‘1’ to AD1BUSY and is followed by the conversion.
010: Tracking started by the overflow of Timer 3 and is followed by the conversion.
100: ADC1 conversion starts on rising CNVSTR1 edge.
110: Tracking started by the overflow of Timer 2 and is followed by the conversion.
xx1: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion.
See Figure 5.4 and Table 5.1 for conversion timing parameters.
RESERVED: Write to 0b.
AD1TM
R/W
Bit6
AD1INT AD1BUSY
R/W
Bit5
Figure 5.10. ADC1CN: ADC1 Control Register
R/W
Bit4
AD1CM2
Rev. 1.2
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
AD1CM1
R/W
Bit2
AD1CM0
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
-
Bit Addressable
0xE8
1
Reset Value
00000000
61
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