C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 161

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

13.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes. In Stop mode, the CPU and internal oscillators are stopped, effectively
shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to enter-
ing Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51
performs the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD
timeout of 100 µs.
Bits7-2:
Bit1:
Bit0:
R/W
Bit7
-
Reserved.
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
IDLE: IDLE Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
and all peripherals remain active.)
See Note in Section
R/W
Bit6
-
R/W
Bit5
-
“13.4.1. Idle
Figure 13.25. PCON: Power Control
R/W
Bit4
-
Mode” on page 160.
Rev. 1.2
R/W
Bit3
-
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
-
STOP
R/W
Bit1
SFR Address:
SFR Page:
IDLE
R/W
Bit0
0x87
All Pages
Reset Value
00000000
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