C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 81

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

Bit 7:
Bit 6:
Bits 5-4: RESERVED. Write to 00b.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SFR Page:
SFR Address:
DMA0HLT DMA0XBY
R/W
Bit7
DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only).
0: DMA0 has complete access to off-chip XRAM.
1: Processor core has complete access to off-chip XRAM. DMA0 will wait until this bit is ‘0’
before writing to off-chip XRAM locations.
DMA0XBY: Off-chip XRAM Busy Flag (C8051F060/2/4/6 Only).
0: DMA0 is not accessing off-chip XRAM.
1: DMA0 is accessing off-chip XRAM.
DMA0CIE: Repeat Counter Overflow Interrupt Enable.
0: Disable Repeat Counter Overflow Interrupt.
1: Enable Repeat Counter Overflow Interrupt.
DMA0CI: Repeat Counter Overflow Flag.
0: Repeat Counter Overflow has not occured.
1: Repeat Counter Overflow has occured. This bit must be cleared by software.
DMA0EOE: End-Of-Operation Interrupt Enable.
0: Disable End-Of-Operation Interrupt.
1: Enable End-Of-Operation Interrupt.
DMA0EO: End-Of-Operation Flag.
0: End-Of-Operation Instruction has not been received.
1: End-Of-Operation Instruction has been received. This bit must be cleared by software.
3
0xF8
Bit6
R
(bit addressable)
Figure 6.5. DMA0CF: DMA0 Configuration Register
R/W
Bit5
-
R/W
Bit4
-
DMA0CIE
Rev. 1.2
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
DMA0CI
R/W
Bit2
DMA0EOE DMA0EO
R/W
Bit1
R/W
Bit0
Reset Value
00000000
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