C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 90

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
7.2.2. Tracking Modes
The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2
input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1,
ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini-
tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion
begins on the rising edge of CNVSTR2 (see Figure 7.3). Tracking can also be disabled (shutdown) when
the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when
AMUX settings are frequently changed, due to the settling time requirements described in
“7.2.3. Settling Time Requirements” on page
90
Timer 3, Timer 2 Overflow
(AD2CM[1:0]=00, 01, 11)
Write '1' to AD2BUSY,
(AD2CM[1:0]=10)
Figure 7.3. 10-Bit ADC Track and Conversion Example Timing
SAR Clocks
SAR Clocks
SAR Clocks
AD2TM=1
AD2TM=0
CNVSTR2
AD2TM=1
AD2TM=0
Low Power
or Convert
Low Power
or Convert
Track or
Convert
A. ADC2 Timing for External Trigger Source
Track or Convert
B. ADC2 Timing for Internal Trigger Source
91.
1
1
Rev. 1.2
Track
2
2
Track
3
3
4
4
1
Convert
5
5
2
6
6
3
7
7
4
Convert
8
8
Convert
Convert
5
9
9
6
10 11 12
10 11
7
8
9
13 14
10 11
Low Power Mode
Track
Low Power
Mode
Track
Section