C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 25

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

1.1.
1.1.1. Fully 8051 Compatible
The C8051F06x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-
51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop software. The core has all the peripherals included with a standard 8052, including
five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space, and bit-addressable I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.
Number of Instructions
Clocks to Execute
CIP-51™ Microcontroller Core
25
20
15
10
Figure 1.5. Comparison of Peak MCU Execution Speeds
5
26
1
(25 MHz clk)
Silicon Labs
CIP-51
50
2
(33 MHz clk)
PIC17C75x
2/3
Microchip
Rev. 1.2
5
C8051F060/1/2/3/4/5/6/7
14
3
(33 MHz clk)
Philips
80C51
3/4
7
4
3
(16 MHz clk)
ADuC812
8051
4/5
1
5
2
8
1
25