C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 324

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
C8051F060/1/2/3/4/5/6/7
324
This register holds the address for all JTAG Flash read, write, and erase operations. This register auto-
after each read or write, regardless of whether the operation succeeded or failed.
Bits15-0: Flash Operation 16-bit Address.
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9-2:
Bit1:
Bit0:
Bit15
Bit9
increments
DATA7-0: Flash Data Byte.
FAIL: Flash Fail Bit.
0: Previous Flash memory operation was successful.
1: Previous Flash memory operation failed. Usually indicates the associated memory loca-
tion was locked.
BUSY: Flash Busy Bit.
0: Flash interface logic is not busy.
1: Flash interface logic is processing a request. Reads or writes while BUSY = 1 will not ini-
tiate another operation
Figure 26.5. FLASHADR: JTAG Flash Address Register
Figure 26.4. FLASHDAT: JTAG Flash Data Register
Rev. 1.2
Bit0
Bit0
0000000000
Reset Value
Reset Value
0x0000

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