C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 246

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
nized. Otherwise, the general call address is ignored. The contents of this register are ignored when
SMBus0 is operating in master mode.
20.4.5. Status Register
The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 inter-
face. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most
significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at
zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta-
tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code
to service the state or jump to a more extensive service routine).
246
Bits7-1:
Bit0:
SLV6
R/W
Bit7
SLV6-SLV0: SMBus0 Slave Address.
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper-
ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address
and corresponds to the first bit of the address byte received.
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
SLV5
R/W
Bit6
Figure 20.11. SMB0ADR: SMBus0 Address Register
SLV4
R/W
Bit5
SLV3
R/W
Bit4
Rev. 1.2
SLV2
R/W
Bit3
SLV1
R/W
Bit2
SLV0
R/W
Bit1
SFR Address:
SFR Page:
R/W
GC
Bit0
0xC3
0
Reset Value
00000000