C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 155
C8051F060_07
Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.C8051F060_07.pdf
(328 pages)
- Current page: 155 of 328
- Download datasheet (3Mb)
Bits7-6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
-
UNUSED. Read = 11b, Write = don't care.
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
R/W
Bit6
-
PT2
R/W
Bit5
Figure 13.20. IP: Interrupt Priority
PS0
R/W
Bit4
Rev. 1.2
PT1
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
PX1
R/W
Bit2
R/W
PT0
Bit1
SFR Address:
SFR Page:
PX0
R/W
Bit0
0xB8
All Pages
Addressable
Reset Value
11000000
Bit
155
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