C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 235

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

20.
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus0 interface autonomously control-
ling the serial transfer of the data. A method of extending the clock-low duration is available to accommo-
date devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation.
SMBUS
IRQ
System Management BUS / I2C BUS (SMBUS0)
S
L
V
6
S
L
V
5
SMB0ADR
S
L
V
4
B
U
S
Y
Interrupt
Request
B
S
L
V
3
M
E
N
S
B
7
S
L
V
2
SMB0CN
S
T
A
A
S
L
V
1
O
S
T
S
L
V
0
S
I
G
C
A
A
F
T
E
B
O
T
E
SFR Bus
0000000b
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
A
7 MSBs
S
A
T
7
S
A
SFR Bus
T
6
SMB0STA
S
T
A
5
S
T
A
4
8
Figure 20.1. SMBus0 Block Diagram
S
T
A
3
SMB0DAT
S
T
A
2
Read
S
T
A
1
7
S
T
A
0
6
8
SMB0DAT
5
4
C
R
7
3
C
R
6
Clock Divide
Data Path
8
Control
2
SMB0CR
C
R
5
Logic
1
SMB0DAT
Rev. 1.2
C
R
4
Write to
0
C
R
3
C
R
2
C
R
1
Control
C8051F060/1/2/3/4/5/6/7
C
R
0
SDA
Control
SCL
1
0
SYSCLK
FILTER
FILTER
N
N
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O
235