C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 292

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
C8051F060/1/2/3/4/5/6/7
292
Bit7:
Bit6:
Bits5-4:
Bit3:
Bit2:
Bits1-0:
GATE1
R/W
Bit7
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic 1.
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic 1.
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T1M1
T0M1
0
0
1
1
0
0
1
1
C/T1
R/W
Bit6
T1M0
T0M0
0
1
0
1
0
1
0
1
T1M1
R/W
Bit5
Figure 24.5. TMOD: Timer Mode Register
Mode 2: 8-bit counter/timer with auto-
Mode 2: 8-bit counter/timer with auto-
Mode 3: Two 8-bit counter/timers
T1M0
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
R/W
Bit4
Mode 3: Timer 1 inactive
Rev. 1.2
GATE0
reload
reload
Mode
Mode
R/W
Bit3
C/T0
R/W
Bit2
T0M1
R/W
Bit1
SFR Address:
SFR Page:
T0M0
R/W
Bit0
0x89
0
Reset Value
00000000

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