C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 135

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
While CIP-51 executes in-line code (writing values to Port 5 in this example), ADC2 Window Comparator
Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR
Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to access
ADC2’s SFRs is then automatically placed in the SFRPAGE register (SFR Page 0x02). SFRPAGE is con-
sidered the “top” of the SFR Page Stack. Software can now access the ADC2 SFRs. Software may switch
to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to
access SFRs that are not on SFR Page 0x02. See Figure 13.5 below.
Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs
SFRPAGE
SFRNEXT
pushed to
SFRPAGE on ADC2
pushed on stack in
SFR Page 0x02
(ADC2)
(Port 5)
Automatically
0x02
0x0F
interrupt
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
SFRPAGE
SFRNEXT
SFRLAST
135

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