C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 94

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C8051F060_07

Manufacturer Part Number
C8051F060_07
Description
Mixed Signal ISP Flash MCU Family
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
C8051F060/1/2/3/4/5/6/7
94
Bits7-3:
Bits2-0:
SFR Page:
SFR Address:
AD2SC4
R/W
Bit7
AD2SC4-0: ADC2 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where ADSC
refers to the 5-bit value held in bits AD2SC4-AD2SC0. SAR Conversion clock requirements
are given in Table 7.1.
UNUSED. Read = 000b; Write = don’t care.
2
0xBC
ADSC
AD2SC3
R/W
Bit6
=
SYSCLK
--------------------- - 1
CLK
Figure 7.7. ADC2CF: ADC2 Configuration Register
AD2SC2
R/W
Bit5
SAR
AD2SC1
R/W
Bit4
AD2SC0
Rev. 1.2
R/W
Bit3
R/W
Bit2
-
R/W
Bit1
-
R/W
Bit0
-
Reset Value
11111000

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