C8051F060_07 SILABS [Silicon Laboratories], C8051F060_07 Datasheet - Page 288

• Manufacturer Part Number: C8051F060_07
• Description: Mixed Signal ISP Flash MCU Family
• Manufacturer: SILABS [Silicon Laboratories]

C8051F060/1/2/3/4/5/6/7
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 205
configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When
T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source
selected by the Clock Scale bits in CKCON (see Figure 24.6).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /
INT0 (see
ments.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1.
288
/INT0
T0
Crossbar
Section “13.3.5. Interrupt Register Descriptions” on page
Pre-scaled Clock
SYSCLK
TR0
0
1
1
1
GATE0
X = Don't Care
Figure 24.1. T0 Mode 0 Block Diagram
TR0
0
1
GATE0
X
0
1
1
CKCON
M
T
1
0
1
M
T
0
S
C
A
1
S
C
A
Rev. 1.2
0
G
A
T
E
1
C
T
1
/INT0
/
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
154), facilitating pulse width measure-
Counter/Timer
Disabled
Disabled
Enabled
Enabled
(8 bits)
for information on selecting and
TH0
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
Section