S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 12

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

1.3
12
Pin Description
Notes:
1. A 0.1 µF capacitor should be connected between the V
2. An internal voltage detector disables all functions whenever V
I/O8 - I/O15 (x16)
I/O0 - I/O7 (x8)
the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
program/erase during power transitions.
Pin Name
WE#
WP#
R/B#
VCC
CLE
ALE
CE#
RE#
VSS
NC
Spansion
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid t
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage. The V
prevents the insertion of Commands when V
Ground.
Not Connected.
Figure 1.4 63-VFBGA Contact, x16 Device (Balls Down, Top View)
REA
®
after the falling edge of RE# which also increments the internal column address counter by one.
SLC NAND Flash Memory for Embedded
CC
NC
NC
NC
NC
A1
B1
M1
L1
supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
A2
NC
M2
L2
NC
NC
Table 1.2 Pin Description
D a t a
CC
WP#
VCC
I/O8
I/O9
NC
V
C3
D3
E3
NC
F3
NC
G3
H3
K3
J3
SS
Supply Voltage pin and the V
CC
CC
VCC
RE#
ALE
I/O0
I/O1
I/O2
NC
NC
G4
C4
D4
E4
F4
H4
J4
K4
is below 1.8V (3V device) to protect the device from any involuntary
is less than V
S h e e t
I/O10
I/O11
VSS
CLE
NC
I/O3
NC
NC
G5
Description
C5
D5
E5
F5
H5
J5
K5
I/O13
I/O12
CE#
V
I/O4
NC
NC
NC
G6
C6
D6
E6
F6
H6
J6
K6
CC
LKO
.
I/O15
I/O14
WE#
VSS
I/O5
I/O6
C7
D7
NC
NC
G7
H7
E7
F7
J7
K7
SS
Ground pin to decouple the current surges from
S34ML01G1_04G1_15 March 7, 2013
RB#
I/O7
NC
V
V
C8
D8
NC
E8
NC
F8
NC
G8
H8
K8
J8
SS
cc
NC
NC
NC
NC
A9
B9
M9
L9
A10
NC
B10
NC
M10
L10
NC
NC