S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 39

no-image

S34ML02G100BHI003

Manufacturer Part Number
S34ML02G100BHI003
Description
Flash 2G, 3V, 25ns NAND Flash
Manufacturer
Spansion
Datasheet

Specifications of S34ML02G100BHI003

Rohs
yes
Data Bus Width
1 bit
Memory Type
NAND Flash
Memory Size
2 Gbit
Architecture
Sectored
Timing Type
Asynchronous
Access Time
25 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
40 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-63
Organization
2048 B x 8, 2048 B x 16
4.3
March 7, 2013 S34ML01G1_04G1_15
Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about
100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of
memory cells being altered are no longer valid, as the data will be partially programmed or erased. The
R/B# pin will stay low for t
register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7
value will be related to the WP# value. Refer to
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to
issuing the setup commands (80h or 60h). The level of WP# shall be set t
for the set up command, as explained in
Figure 4.2 WP# Low Timing Requirements during Program/Erase Command Sequence
D a t a
RST
Spansion
I/O[7:0]
(similarly to
WP#
WE#
S h e e t
®
SLC NAND Flash Memory for Embedded
Figure 6.40
Figure 6.26 on page
> 100 ns
Table 3.5 on page 29
and
Figure 6.41 on page
Valid
56). At the end of this time, the command
Sequence
for more information on device status.
Aborted
WW
ns prior to raising the WE# pin
64.
39

Related parts for S34ML02G100BHI003