S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 73

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

March 7, 2013 S34ML01G1_04G1_15
Copy Back Program
Multiplane Copy Back Program —
S34ML02G1 and S34ML04G1
Read ID2
Read ONFI Signature
Read Parameter Page
One-Time Programmable (OTP) Entry
Program/Erase Characteristics
Timing Diagrams
Revision 07 (July 23, 2012)
Command Set
Read Parameter Page
Valid Blocks
DC Characteristics
Revision 08 (August 2, 2012)
Global
Read Parameter Page
Physical Interface
Ordering Information
Appendix A
Revision 09 (August 29, 2012)
Global
Revision 10 (September 6, 2012)
Connection Diagram
Command Set
AC Characteristics
Revision 11 (October 1, 2012)
Addressing
Multiplane Program — S34ML02G1 and
S34ML04G1
Block Erase
Section
Updated section
Updated section
Added section
Added Section
Note that all ONFI information is in the Advanced Information designation
Added section
Note that all ONFI information is in the Advanced Information designation
Added section
Note that all ONFI information is in the Advanced Information designation
Added note to table
Rearranged section
Added timing diagrams: Multiplane Block Erase (ONFI 1.0 Protocol), Multiplane Cache Program
(ONFI 1.0 Protocol), Read ID2 Operation Timing, ONFI Signature Timing, Read Parameter Page
Timing, Read ID2 Operation Timing, OTP Entry Timing
Updated timing diagrams: Page Read Operation (Read One Page), Page Read Operation
Intercepted by CE#, Page Read Operation Timing with CE# Don’t Care, Page Program Operation,
Page Program Operation Timing with CE# Don’t Care, Random Data Input, Random Data Output,
Multiplane Page Program, Block Erase Operation (Erase One Block), Reset Operation Timing, Read
Cache Operation Timing, Cache Program, Multiplane Cache Program, Read ID Operation Timing
Note that all ONFI information is in the Advanced Information designation
Command Set table: changed Read ONFI Signature to ‘Yes’ for Supported on S34ML01G1
Parameter Page Description table: changed Byte 254-255 Values
Valid Blocks table: removed Note 1 and Note 3
DC Characteristics and Operating Conditions table:
Note that all ONFI information is now in the Preliminary designation
Parameter Page Description table: updated values for bytes 6-7, 108-109, 254-255
Added TSOP (2 CE 8 Gb) diagram
Added BGA diagram
Updated data
Added Errata
Removed 8 Gb data
Added x16 I/O bus width data
48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts
63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pinouts, removed note
Reorganized section
Corrected T
Address Cycle Map — 1 Gb Device: corrected data
Address Cycle Map — 2 Gb Device: corrected data
Address Cycle Map — 4 Gb Device: corrected data
Added text
Added text
corrected Output low voltage Test Conditions
corrected Output low current (R/B#) Typ and Max values
D a t a
Spansion
ALS
Min and T
S h e e t
®
SLC NAND Flash Memory for Embedded
DS
Min
Description
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