S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 22

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.3
22
Multiplane Program — S34ML02G1 and S34ML04G1
The S34ML02G1 and S34ML04G1 devices support Multiplane Program, making it possible to program two
pages in parallel, one page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (x8) or
2112 words (x16) of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell. The serial data loading period begins with
inputting the Serial Data Input command (80h), followed by the five cycle address inputs and serial data for
the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device supports Random
Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (t
become ready again, the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its
serial data input. The address for this page must be in the 2nd plane (PLA0 = 1). The Program Confirm
command (10h) starts parallel programming of both pages.
Figure 6.13 on page 49
bits for the first plane are all zero and the second address issued selects the block for both planes.
Figure 6.14 on page 50
protocol, the block address bits must be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or
78h). The Read Status Register command is also available during Dummy Busy time (t
failure in either page program, the fail bit of the Status Register will be set. Refer to
further info.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in
within a block.
If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted pages are not used for further reading or programming operations until the
next uninterrupted block erases are complete for the applicable blocks.
Spansion
®
describes the sequences using the legacy protocol. In this case, the block address
describes the sequences using the ONFI protocol. For both addresses issued in this
SLC NAND Flash Memory for Embedded
Table 5.7 on page
D a t a
43. In addition, pages must be programmed sequentially
S h e e t
S34ML01G1_04G1_15 March 7, 2013
Section 3.9 on page 28
DBSY
DBSY
). In case of
). Once it has
for