S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 59

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S34ML02G100BHI003

Manufacturer Part Number
S34ML02G100BHI003
Description
Flash 2G, 3V, 25ns NAND Flash
Manufacturer
Spansion
Datasheet

Specifications of S34ML02G100BHI003

Rohs
yes
Data Bus Width
1 bit
Memory Type
NAND Flash
Memory Size
2 Gbit
Architecture
Sectored
Timing Type
Asynchronous
Access Time
25 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
40 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-63
Organization
2048 B x 8, 2048 B x 16
6.25
March 7, 2013 S34ML01G1_04G1_15
Multiplane Cache Program — S34ML02G1 and S34ML04G1
Note:
1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.
RY/BY#
RY/BY#
R/B#
WE#
R/B#
CLE
ALE
WE#
CE#
RE#
CLE
ALE
CE#
RE#
I/Ox
I/Ox
1
1
Command Input
Command Input
80h
80h
80h
80h
tWB
tWB
Add1
Col.
Column Address
Column Address
Add1
Col.
Address Input
Address Input
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
Add2
Col.
Add2
Col.
Return to 1
Repeat a max of 63 times
Add1
Row
Add1
Row
D a t a
Row Address
Spansion
Add2
Row Address
Row
Row
Add2
Add3
Row
Add3
Row
tADL
Figure 6.32 Multiplane Cache Program
Data Input
Data Input
S h e e t
Din
Din
®
N
N
SLC NAND Flash Memory for Embedded
Din
Din
M
M
11h
11h
tWB
11h
11h
tDBSY
tDBSY
t
t
DBSY
DBSY
81h
81h
81h
81h
tWC
tWC
Column Address
Column Address
Add1
Add1
Col.
Col.
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
Address Input
Address Input
Add2
Col.
Add2
Col.
Add1
Row
Add1
Row
Row Address
Row Address
Add2
Row
Add2
Row
Add3
Row
Row
Add3
tADL
Data Input
Data Input
Din
N
Din
N
Din
Din
M
M
15h
10h
10h
15h
tPROG
tCBSYW
t
t
PROG
70h
CBSYW
I/O
Q
1
1
59

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