S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 37

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.20
4. Signal Descriptions
4.1
March 7, 2013 S34ML01G1_04G1_15
One-Time Programmable (OTP) Entry
Data Protection and Power On / Off Sequence
Note:
1. O” Stands for Optional, “M” for Mandatory.
The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to
the command register. The device is then ready to accept Page Read and Page Program commands (refer to
Page Read
hence only row addresses between 00h and 3Fh are allowed. The host must issue the Reset command (refer
to
not allowed in the OTP area. Refer to
sequence.
The device is designed to offer protection from any involuntary program/erase during power-transitions. An
internal voltage detector disables all functions whenever V
The power-up and power-down sequence is shown in
the one hand (and V
The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum
values (as specified on), and shall return to one within 5 ms (max).
During this busy time, the device executes the initialization process (cam reading), and dissipates a current
I
At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page
read command, the 00h command may be skipped.
The WP# pin provides hardware protection and is recommended to be kept at V
power-down. A recovery time of minimum 100 µs is required before the internal circuit gets ready for any
command sequences as shown in
program/erase provides additional software protection.
CC0
166-253
254-255
256-511
512-767
Reset on page
Byte
768+
(30 mA max), in addition, it disregards all commands excluding Read Status Register (70h).
O/M
and
M
M
M
O
Page Program on page
29) to exit the OTP area and access the normal flash array. The Block Erase command is
Integrity CRC
Vendor specific
Value of bytes 0-255
Value of bytes 0-255
Additional redundant parameter pages
SS
and V
D a t a
Table 3.12 Parameter Page Description (Sheet 3 of 3)
Spansion
SSQ
on the other hand) are shorted together at all times.
Figure 6.39 on page
S h e e t
®
Figure 6.38 on page 63
SLC NAND Flash Memory for Embedded
21). The OTP area is of a single erase block size (64 pages), and
Redundant Parameter Pages
Description
Figure 6.39 on page
63. The two-step command sequence for
CC
is below about 1.8V (3V device).
for more detail on the OTP Entry command
63, in this case V
IL
during power-up and
00h
S34ML01G100 (x8): E9h, 0Ah
S34ML02G100 (x8): 3Bh, C5h
S34ML04G100 (x8): 45h, 8Eh
S34ML01G104 (x16): 9Bh, 7Ch
S34ML02G104 (x16): 49h, B3h
S34ML04G104 (x16): 37h, F8h
Repeat Value of bytes 0-255
Repeat Value of bytes 0-255
FFh
CC
Values
and V
CCQ
on
37