S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 25

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.6
3.7
March 7, 2013 S34ML01G1_04G1_15
Multiplane Block Erase — S34ML02G1 and S34ML04G1
Copy Back Program
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. In this
case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion. See
Table 5.7 on page 43
For the Multiplane Block Erase operation, the address of the first block must be within the first plane
(PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See
for a description of the legacy protocol. In this case, the block address bits for the first plane are all zero and
the second address issued selects the block for both planes.
sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits must
be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or
78h). The Read Status Register command is also available during Dummy Busy time (t
failure in either erase, the fail bit of the Status Register will be set. Refer to
info.
If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted blocks are erased under continuous power conditions before those blocks
can be trusted for further programming and reading operations.
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the
system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to
be updated and the rest of the block also needs to be copied to the newly assigned free block. The operation
for performing a copy back is a sequential execution of page-read (without mandatory serial access) and
Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole 2112-byte (x8) or 1056-word (x16) data into the internal data
buffer. As soon as the device returns to Ready state, optional data read-out is allowed by toggling RE# (see
Figure 6.18 on page
may be written. The Program Confirm command (10h) is required to actually begin the programming
operation.
Source and Destination page in the Copy Back Program sequence must belong to the same device plane
(same PLA0 for S34ML02G1 and S34ML04G1). Copy Back Read and Copy Back Program for a given plane
must be between odd address pages or between even address pages for the device to meet the program
time (t
address page (source page) to an even address page (target page) or from an even address page (source
page) to an odd address page (target page).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as
shown in
(for S34ML02G1 and S34ML04G1) check during the copy back operation, to detect single bit errors in EDC
units contained within the source page. More details on EDC operation and limitations related to data input
handling during one Copy Back Program sequence are available in
If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host
must ensure that the interrupted page is not used for further reading or programming operations until the next
uninterrupted block erase is complete.
PROG
Figure 6.19 on page
) specification. Copy Back Program may not meet this specification when copying from an odd
52), or Copy Back Program command (85h) with the address cycles of destination page
for performance information.
D a t a
Spansion
52. As noted in
S h e e t
®
SLC NAND Flash Memory for Embedded
Section 1. on page 9
Figure 6.17 on page 51
the device may include an automatic EDC
Section 3.8 on page
Section 3.9 on page 28
Figure 6.16 on page 51
describes the
DBSY
26.
). In case of
for further
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