S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 44

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

6.2
6.3
44
Address Latch Cycle
Data Input Cycle Timing
Address Input bus operation allows the insertion of the memory address. To insert the 27 (x8 Device)
addresses needed to access the 1 Gb, four write cycles are needed. Addresses are accepted with Chip
Enable low, Address Latch Enable High, Command Latch Enable low, and Read Enable High and latched on
the rising edge of Write Enable. Moreover, for commands that start a modify operation (write/ erase) the Write
Protect pin must be high.
Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serially, and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising
edge of Write Enable.
WE#
CLE
CE#
ALE
I/Ox
Spansion
WE#
CLE
CE#
ALE
I/Ox
®
tCS
tCLS
SLC NAND Flash Memory for Embedded
tALS
tWP
tDS
Add1
Col.
tWC
tALH
tDH
tALS
tWH
Figure 6.3 Input Data Latch Cycle
tWP
Figure 6.2 Address Latch Cycle
tDS
Din 0
tWC
tDH
tALS
tWH
D a t a
tWP
tDS
Add2
Col.
tWC
tALH
tDH
tWP
tWH
tDS
S h e e t
Din
tDH
tWH
tALS
tWP
tDS
Row.
Add1
tWC
tALH
tWP
tDH
Din final
tDS
tWH
S34ML01G1_04G1_15 March 7, 2013
tDH
tCH
tCLH
tALS
tWP
tDS
Row.
Add2
tALH
tWC
tDH
tWH
tALS
tDS
Row.
Add3
tDH
tALH